Grabinski Modeling Consulting

• Leading edge CMOS technology support through partners in-house process development
• Custom engagements in advanced IDM/IP for both OEM and fabless chip companies
  
• Development and support of the parameter extraction packages for state-of-the-art compact models:
• BSIM Standard
  
• EKV Standard
  
• HiSIM and LDMOS
  
• PSP with JANCAP
• Model parameter extraction with a special emphasis on low power (LP, LV) and analog/RF designs
• Model QA validation following CMC, GSA and IEEE test procedure #P1485 recommendations
  
• Vendor component and design libraries generation for advanced CMOS technologies
• OpenSource compact modeling solutions based on Verilog-A coding
• Modeling events organization:
• MOS-AK Association
• ESSDERC/ESSCIRC Workshops
• DATE Workshops
  
• MIXDES special modeling sessions

Reference Modeling Books:		Partner's CAD Tools/CMOS Technologies
	Transistor Level Modeling for Analog/RF IC Design W.Grabinski,B.Nauwelaers,D.Schreurs Publisher: Mark.deJongh@springer-sbm.com ISBN: 1-4020-4555-7 (2006) www.springer.com	Develops IC-CAP the standard for parameter extractions
	Transistor Level Modeling for Analog/RF IC Design Editors: W.Grabinski,B.Nauwelaers,D.Schreurs ISBN: 978-7-03-018241-8 (2007) www.sciencep.com	Pure-Play Foundry	Delivers state of the art design enablement solutions
	Power/HVMOS Devices Compact Modeling Editors: W.Grabinski, T.Gneiting Publisher: Mark.deJongh@springer-sbm.com ISBN: 978-90-481-3045-0 (2010) www.springer.com	Research Center for the High-Tech Industry	Innovation for High Performance Microelectronics
	M. Najmzadeh, Y. Tsuchiya, D. Bouvet, W. Grabinski and M. A. Ionescu. Multi-Gate Buckled Self-Aligned Dual Si Nanowire MOSFETs on Bulk Si for High Electron Mobility, in IEEE Transactions on Nanotechnology, vol. 11, p. 902-906, 2012.
	Open Source CAD for Compact Modeling Editors: W.Grabinski, D.Tomaszewski Publisher: springer-sbm.com ISBN: 978-90-481-xxxx-0 (expt.2017) www.springer.com

Update: Oct. 2024 (rev.a) wladek@grabinski.ch